1. Field of the Invention
The present invention relates to a film carrier and a method for manufacturing the same. More particularly, the invention relates to a film carrier and a method that can prevent a short-circuit between inner leads and edge portions of a semiconductor chip by anodizing end portions of the inner leads contacting an electrode pad of the semiconductor chip.
2. Description of the Related Art
In general, semiconductor chips such as integrated circuits (IC) or large scale integrated circuits (LSI) are very thin and small-sized and thus cannot be mounted directly to a printed circuit board (PCB). Accordingly, the semiconductor chips are encapsulated in a molding resin to be mounted in the PCB.
Generally, the basic structure of a semiconductor package is as follows. A semiconductor chip is mounted on a die pad of a lead frame to connect an electrode terminal of the semiconductor chip to leads for connecting an outer circuit by a bonding wire. The semiconductor chip and the bonding wire are sealed together with the lead frame, and a plurality of outer leads are extended from the package.
Such semiconductor packages are mainly divided into a dual in-line package (DIP) having two rows of leads which are bent vertically and downwardly from both sides of the semiconductor package and a quad flat package (QFP) having two rows of staggered pins on each of four sides of the semiconductor package. The QFP has the advantage that it can be more densely mounted on the PCB than the DIP can.
Recently, as electronic appliances of high functionality, small-size and light weight are becoming increasingly popular, semiconductor ships have become highly integrated, and the number of pins are increased correspondingly. Hence, packages made by wire-bonding such as DIPs and QFPs are not satisfactory any more, and a new package is now required.
Therefore, there has been improved a film carrier in which an electrode of a semiconductor chip and corresponding leads are collectively connected to each other, instead of a conventional wirebonding method. This method for manufacturing the film carrier is also known as the tape carrier method, or the tape automated bonding method (TAB).
The film carrier method is a kind of surface-mounting package technique, in which a lead frame and metallic patterns (leads) serving as the conducting wire are formed on a base film, and metallic patterns on the base film are bonded to an electrode pad of the semiconductor chip by bumps formed of metallic protrusions. This film carrier method of an advanced technology is totally different from the bonding-wire method, and is mainly used in a small-sized electric calculator, liquid crystal displays (LCD), computers, etc.
FIG. 1 is a plan view of a film carrier used in a TAB package according to the prior art.
Referring to FIG. 1, the conventional film carrier is provided with an insulating film having sprocket apertures 12, inner leads 22 and outer leads 24 formed by photo-etching a copper thin film attached to this insulating film 10. The inner leads 22 and outer leads 24 are generally referred to as leads 20, hereinafter. The insulating film 10 is made of polyester, polyethersulfonate (PES), polyparaanic acid (PPA).
The manufacturing process for making the above film carrier is generally described in detail as follows.
First, the insulating film 10 is punched to form a device hole 16 and outer lead grooves 14, and a thin copper film is deposited on the insulating film to a thickness of 18-35 .mu.m. Subsequently, a photosensitive layer is applied to the thin copper film, exposed to light, and then developed to form a pattern of the photosensitive layer. Thereafter, the exposed area of the thin copper film is etched by using the pattern of the photosensitive layer, which is removed later.
Accordingly, the inner leads 22 and outer leads 24 are formed by patterning of the photosensitive layer. The inner leads 22, which partially extend into the device hole 16 are formed to be straight near the edge of the insulating film 10. Such a film carrier is formed by a series of film carrier units of the same structure, and can be kept together by being wound on a reel. On the film carrier, semiconductor chips are mounted in various ways. That is to say, after an electrode pad of a semiconductor chip is joined to ends of the inner leads 22 by simultaneous multi point bonding (namely gang bonding), the ends of the outer lead 24 are joined to metallized electrodes of the PCB.
FIGS. 2 and 3 are partially sectional views showing a method for bonding an electrode pad of a semiconductor chip and inner leads mounted in the film carrier of FIG. 1.
Referring to FIG. 2, a bump 34 of gold (Au) is formed on the electrode pad 32 of the semiconductor chip 30, and the inner lead 22 corresponding thereto is placed on the bump 34. After that, the electrode pad 32 of the semiconductor chip 30 is joined to the inner lead 22 by the bump 34 spread out by a thermo-compression method.
The bump 34, which is generally formed on the electrode pad 32 of the semiconductor chip 30, can be formed on the inner lead 22 disposed to be corresponding to the electrode pad 32. The PCB or a LCD is coupled to the outer lead 24. Here, reference numeral 10 in FIG. 2 designates an insulating film. Such a technique is disclosed in U.S. Pat. Nos. 4,494,688 and 3,763,404, hereby incorporated by reference.
The bonding technique using the bump as shown in FIG. 2 requires an expensive and precise apparatus due to fine pitch between the electrode pads 32 according to the high integration in the process of forming the bump 34 on the electrode pad 32 of the semiconductor chip 30. Besides this fact, the method has another disadvantage in that the inner lead 22 connected electrically to the electrode pad 32 may be short-circuited at the edge of the semiconductor chip 30, though the inner lead 22 connected to the electrode pad 32 by the bump 34 is off form the surface of the semiconductor chip 30 as munch as the height of the bump 34.
Another bonding technique, which is disclosed in U.S. Pat. No. 4,210,926, hereby incorporated by reference, is a direct bonding technique in which the electrode pad of the semiconductor chip is bonded to the inner lead without the bump, as shown in FIG. 3.
Referring to FIG. 3, the inner lead 22 formed on the insulating film 10 is provided with a contact portion 22a bonded to the electrode pad of the semiconductor chip and an edge portion 23 of a corresponding position to the edge portion 8 of the semiconductor chip.
According to the above bonding technique, the inner lead 22 is placed on the electrode pad 32 of the semiconductor chip 30 to come into contact with the contact portion 22a, and the electrode pad 32 of the semiconductor chip 30 is bonded to the inner lead 22 by a thermo-compression method.
Such a bonding technique has an advantage in that it requires no bump, but it also has a disadvantage in that it requires a precise etching process of edge portion 23 without failure in order to prevent a short-circuit that may occur at the edge portion of the semiconductor chip 30.
In addition, the above bonding technique has another disadvantage in that it cannot exactly etch the end of the finely-pitched inner lead 22 to a suitable thickness, and that the end of the inner lead 22 is degraded by the contact portion 22a which remains thin after the etching process.